Accelerating AI Using Next-Generation Hardware: Possibilities and Challenges With Analog In-Memory Computing

Marcus Valtonen Örnhag, Püren Güler, Dmitry Knyaginin, Mattias Borg; Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision (WACV) Workshops, 2023, pp. 488-496

Future generations of computing systems need to continue increasing processing speed and energy efficiency in order to meet the growing workload requirements under stringent environmental constraints. As a result, domain-specific hardware accelerators and platforms have become widely used. In addition to the conventional approach, where memory and processing elements are separated, an emerging approach called in-memory computing (IMC) is being actively researched. IMC co-locates memory and processing, which reduces data transfer energy and thus promises to increase energy efficiency. Unlike digital IMC, analog IMC performs operations like multiplication and addition in the analog domain. It may use new types of devices, manufactured using new materials that offer higher scalability. Despite being actively researched, limited knowledge is available about their performance on common computing tasks. In this paper, we analyze the performance of analog IMC devices on two imaging problems: image denoising and semantic segmentation. In both cases, we use deep learning-based algorithms and show how the performance varies between the applications as well as discuss the effects of internal and external noise sources. Our insights can help to select a suitable application for analog IMC devices, reason about their performance, and understand the application-specific requirements for a desired level of performance. Thus, they further function as input to future analog IMC device manufacturers.